1. Field of the Invention
The present invention relates to data transmission. Specifically, the following discloses a method and circuit for issuing a signal which indicates that all of the information in a burst transmission of data has been sent.
2. Description of Related Art
Data busses are used to transfer data between components in a computer system. A number of different standards for these buses have been implemented to facilitate and standardize the protocols used in the transmission and reception of data over these buses. Such standardization allows components from different manufacturers to communicate.
One of those standards, the Peripheral Component Interconnect, PCI, standard has gained widespread popularity. One feature of the PCI standard is that it facilitates high speed data transmission using burst transfers. A burst transfer comprises an address phase and one or more data phases. In a burst access, up to 32 bits or 64 bits can be transferred each clock depending upon if a 32 or 64 bit transfer cycle is in progress and what byte enables are asserted.
PCI data transfers are controlled with three fundamental signals. A FRAME# signal, controlled by a master being the source of the data indicates the beginning and end of a burst transfer. An IRDY# signal indicates when the master is ready to transfer data and a TRDY# signal indicates when the target (the destination for the data) is ready to receive the data.
The PCI interface is in an idle state when both FRAME# and IRDY# signals are deasserted. The first clock edge on which FRAME# is asserted starts the address phase. The next clock edge begins the first of one or more data phases. During the data phase, data is transferred between master (source) and target (destination) on each clock edge for which IRDY# and TRDY# are asserted. Wait cycles may be inserted in a data phase by either the master (source) or the target (destination) when either the IRDY# signal or the TRDY# signal is deasserted.
The source of the data is required to assert its IRDY# or TRDY# signal unconditionally, when data is valid (IRDY# if a master, TRDY# if a target). The target may delay the assertion of its IRDY# or TRDY# when it is not ready to accept data. Data can only be transferred when IRDY# and TRDY# are both asserted on the same rising clock edge. Once the master has asserted IRDY#, it cannot change IRDY# or FRAME# until the current data phase is completed regardless of the state of TRDY#. Once a target has asserted TRDY#, it cannot change TRDY#, until the current data phase is completed. Thus, neither the master nor the target can change the start and end of a data transfer until a data phase is completed. (A data phase completes when IRDY# and TRDY# or STOP# (which indicates the assertion of a disconnect). Data may or may not transfer depending on the state of TRDY#.
The target can interrupt the data burst with a disconnect signal. An assertion of a disconnect results in the master terminating the access, and getting off the bus. The master may resume the access later. The master might wish to issue 64-bit transfers but the target must agree to this through the protocol. The target may initially agree to a 64-bit transfer at the beginning of a burst but only allow 32-bit transfers after a disconnect when the master returns to complete the transfer. Multiple disconnects can occur during a burst with the 32/64 bit negotiations taking place at the beginning of each resumed access.
At such time as the master intends to complete only one more data transfer (which could be immediately after the address phase), FRAME# is deasserted and IRDY# is asserted or remains asserted indicating the master is ready. After the target indicates that it is ready to complete the final data transfer (TRDY# is asserted), the PCI interface logic returns to the idle state with both FRAME# and IRDY# deasserted. Additional details of the operation of a PCI circuit are contained in PCI Local Bus Specifications available from PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214, (800) 433-5177 (U.S.), (503) 797-4207 (International), and (503) 234-6792 (FAX). The contents of that document are hereby incorporated by reference.
A burst control circuit is used to handle the incoming data transfer signals from the target (e.g. TRDY#, DELSEV#, or STOP#) and to generate control signals (e.g. FRAME#, IRDY#) through the end of a data transfer. In particular, for the master to conduct burst transfers in compliance with the protocol, FRAME# is asserted until the data phase immediately preceding the last data phase needed to complete the burst access. A vital part of the master's control logic is a mechanism which keeps track of how much of the burst transfer has been completed and determines when FRAME# is to be deasserted.
In order to keep up with the higher data transfer rates required by high speed busses, such as the 66 MHz PCI standard data transfer rate, traditional circuits have turned to high speed components to track how much of the burst transfer has been completed and determine when FRAME# is to be deasserted. Such high speed components or the technologies providing them are expensive. For example, high speed adders needed to work in the convention burst control approach add substantial cost to other PCI interface designs. Thus, a lower cost method of handling high speed data transfer is desirable.